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Sample text
Because files are particularly important for simulation, details will be given in chapter 10, which deals specifically with the subject (simulation with testbenches). CONSTANT As the name says, it is an object whose value cannot be changed. A simplified syntax for the declaration of constants is shown below. CONSTANT constant_name: constant_type := constant_value; The name can be essentially any word, except reserved words. The type can be any VHDL type, either predefined or user-defined (seen in the coming sections of this chapter).
Solution A corresponding VHDL code is shown below, with 'Z' employed in the WHEN statement of line 12. While the enable port is asserted (ena ¼ '1'), the input is copied to the output. However, if ena ¼ '0', the bu¤er is physically disconnected from the output node (high-impedance state). Note that the package std_logic_1164 (lines 2–3) is needed because it is in that package that 'Z' is defined (BIT would not do because it can only be '0' or '1'). 4b–c. In the former, all outputs are specified with '0's and '1's, while in the latter there is a ‘‘don’t care’’ output (y ¼ "--").
3, a two-block circuit is shown. The inputs are two unsigned 3-bit values (a and b, ranging from 0 to 7), while the outputs are comp (single bit) and sum (to avoid overflow, 4 bits are needed, hence ranging from 0 to 15). The upper part must com- Code Structure 19 pare a to b, producing a '1' when a > b or '0' otherwise. The lower part must add a and b, producing sum. A VHDL code for this circuit is shown below. Note that dashed lines (lines 1, 4, 10, 16) were used to better organize the code (separating it into the three fundamental sections mentioned earlier).
