By Thaddeus J. Kowalski

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This information is utilized to apply the clock-gating at an appropriate place. The power model is integrated with untimed transaction-level test/application environment, which is shown to be 2–3 orders of magnitude faster than the state-of-the-art RTL power estimation techniques. This helps in analyzing more power reduction opportunities and helps in putting the appropriate granularity of clock-gating. This can also serve as a basis of applying estimation-guided reduction for other optimizations such as sequential clock-gating, operand isolation, memory gating.

It is basically a library of C++ classes that allows RTL as well as high-level modeling using hardware-oriented constructs. Various high-level synthesis tools which take such C-like HDLs as input have also been proposed [104]. Forte’s Cynthesizer [52] and Celoxica’s Agility Compiler [23] are examples of tools which provide synthesis path from high-level SystemC models to RTL. Mentor’s Catapult [82] is a high-level synthesis tool that uses ANSI-C++ to generate RTL code. PICO Express by Synfora [114] synthesizes G.

An HTG is a directed acyclic graph having three types of nodes: (1) single nodes which are non-hierarchical nodes and are used to encapsulate basic blocks; (2) compound nodes which have sub-nodes and are used to represent constructs such as if–then–else blocks, switch-case blocks, or a series of HTGs; and (3) loop nodes which are used to represent various loops such as for, do–while. Loop nodes consist of a loop head and a loop tail that are single nodes and a loop body that is a compound node.

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