By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins
With the previous few decade efforts on lithography and integrated-circuit (IC) applied sciences, very reasonably cheap microsystems were effectively constructed for lots of diverse purposes. the craze in instant communications is towards making a networkubiquitous period within the years yet to come. Many unparalleled possibilities and demanding situations, corresponding to layout for multi-standardability and low-voltage (LV) compliance, are quickly changing into the mainstream instructions in wireless-IC study and improvement, on condition that the previous can provide the simplest connectivity between diversified networks, whereas the latter can facilitate the expertise migration into the sub-1-V nanoscale regimes for additional rate and gear aid.
Analog-Baseband Architecturees and Circuits presents architectural and circuit thoughts for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the publication stories the actual layer requisites of recent instant communique criteria, offers the elemental tradeoffs keen on transceiver structure choice, and gives case reviews of the cutting-edge multistandard transceivers, the place the major options strengthened are highlighted and mentioned. A statistical precis (with a hundred+ references pointed out) of so much used transmitter and receiver architectures for contemporary conversation criteria is supplied. the entire references are citied from the major boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.
The moment half makes a speciality of the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection procedure is disclosed. It, during the reconfiguration of receiver and transmitter analog basebands, allows not just a rest of the RF frequency synthesizer’s and native oscillator’s layout requirements, but in addition a good multistandard compliance through synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the primary is validated in few layout examples. one in all them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but in addition contains a flexible-IF topology, a special 3D-stack floorplan, and a selected layout technique for top testability and routability.
The 3rd half offers with the circuit layout. as well as the methodical description of many LV circuit ideas, three tailormade LV-robust useful blocks are offered. They comprise: 1) a double-quadrature-downconversion filter out (DQDF) – it realizes simultaneously clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon zone required for understanding a wide time consistent on chip whereas maximizing its highpass-pole switchability for speedy dc-offset transient.
The final half offers experimental result of the three tailored construction blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS approach. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the development blocks have effectively prolonged the cutting-edge boundary by way of sign bandwidth and provide voltage, the analog-baseband IC has been up to now the lowest-voltage-reported answer for IEEE 802.11a/b/g WLAN receivers.
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Extra resources for Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers
One frequency synthesizer and one VCO shares between different modes, RX and TX. The LO leakage in the transmitter is eliminated by applying a LO-leakage calibration loop. The lowpass channel-selection filter in both RX and TX is of fifth-order and offers a variable gain feature. A successive switching technique implemented in the dc-offset cancellation loop is to improve the settling time in the RX gain adjustment. Chapter 2: Transceiver Architecture Selection Figure 2-14. R. 11a/b/g transceiver Figure 2-15.
88–89, Feb. 2002. 67] M. 4 GHz RF Transceiver with Digital Channel-Selection Filter for Bluetooth,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 93–94, Feb. 2002. 68] H. 8-V Operation RFCMOS Transceiver for Bluetooth,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 230–233, June 2002. 69] C. , “A 43mW Bluetooth Transceiver with –91dBm Sensitivity,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.
Xu et al. 11a T. Rühlicke et al. 5 mm2 –- –74 dBm 600 mW 465 mW ––85 dBm 345 mW 330 mW –74 dBm 345 mW 330 mW high/low gain, *: no A/D and D/A, +: 54 Mb/s for a, g 11Mb/s for b SUMMARY We have summarized in this chapter some essential information that is worth considering during transceiver architecture selection. Some general conclusions are drawn below: Architecturally, to meet the goals of low power and low cost as well as high integration and multistandard compliance, the superheterodyne architecture should be avoided.