By John M. Cohn, David J. Garrod, Visit Amazon's Rob A. Rutenbar Page, search results, Learn about Author Central, Rob A. Rutenbar, , L. Richard Carley

This publication provides an in depth precis of study on computerized format of device-level analog circuits that was once undertaken within the overdue Eighties and early Nineties at Carnegie Mellon collage. We specialize in the paintings in the back of the construction of the instruments known as KOAN and ANAGRAM II, which shape a part of the middle of the CMU ACACIA analog CAD process. KOAN is a tool placer for customized analog cells; ANANGRAM II an in depth zone router for those analog cells. we try to give the motivations in the back of the structure of those instruments, together with exact dialogue of the delicate know-how and circuit issues that has to be addressed in any profitable analog or mixed-signal structure instrument. Our strategy in organizing the chapters of the e-book has been to give our algo­ rithms as a chain of responses to those very genuine and intensely tricky analog structure difficulties. ultimately, we current a number of examples of effects generated by way of our algorithms. This study was once supported partly by way of the Semiconductor study Corpora­ tion, by means of the nationwide technology starting place, via Harris Semiconductor, and through the overseas enterprise Machines company Resident learn application. ultimately, only for the list: John Cohn used to be the dressmaker of the KOAN placer; David Garrod used to be the fashion designer of the ANAGRAM II router (and its predeces­ sor, ANAGRAM I). This publication used to be architected by way of all 4 authors, edited by way of John Cohn and Rob Rutenbar, and produced in comprehensive shape by way of John Cohn.

Show description

Read or Download Analog Device-Level Layout Automation PDF

Best cad books

Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

Regardless of the outstanding breakthroughs of the semiconductor undefined, the power to layout built-in circuits below stringent time-to-market requisites is lagging in the back of integration potential, thus far maintaining velocity with nonetheless legitimate Moore’s legislations. The ensuing hole is threatening with slowing down this type of extra special progress.

AutoCAD 2000i

Clients advisor for AutoCad 2000i

Verification Methodology Manual for SystemVerilog

Practical verification is still one of many unmarried largest demanding situations within the improvement of advanced system-on-chip (SoC) units. regardless of the creation of successive new applied sciences, the space among layout potential and verification self assurance maintains to widen. the largest challenge is that those various new applied sciences have resulted in a proliferation of verification element instruments, such a lot with their very own languages and methodologies.

A Far-Infrared Spectro-Spatial Space Interferometer: Instrument Simulator and Testbed Implementation

This thesis describes the physics and computational facets of an end-to-end simulator to foretell the functionality of a Space-based a ways Infrared Interferometer. the current thesis additionally contains, the technological know-how functions and instrumental state-of-the artwork. The latter is the bold subsequent step which the Far-Infrared Astrophysical neighborhood must take to enhance by any means at the result of the latest and present area telescopes during this wavelength sector.

Additional info for Analog Device-Level Layout Automation

Sample text

It also insures that the layouts are free of design-rule errors and reserves sufficient inter-device space to allow routing. These are basically the same requirements for digital macro-cell placement. For this reason, many of the placement techniques we describe here, have been adapted from digital placement methods. While these techniques are not necessarily unique to our research, they are combined into a framework which is well suited to handle the analog-specific functionality we introduce in subsequent chapters.

Device Representation Our device representation records the shapes, process layers, positions, and connectivity of all devices in the evolving placement. This information is extracted from the labels in the mask geometry created by the device generators. The method used to represent device geometry is critical to the placer's ability to recognize and eliminate illegal overlap among devices. To achieve our placement goals of manual-like layout density, we use a more detailed representation of device geometry than is used by typical macro-cell placers.

The dimensions of the outline are chosen such that eliminating the overlap of the black-boxes insures that all technology spacing rules are met. 7(a). 7 Examples of black-box device representation (a) device geometry, (b) black-box representation. for the device-level analog placement problem for two reasons. First, because the black-box representation is opaque to the placer, it abstracts away all of the devices internal structure, and thus precludes the ability to recognize certain forms of overlap as potentially beneficial cases of geometry sharing.

Download PDF sample

Rated 4.49 of 5 – based on 7 votes