By Taoufik Bourdi
During this ebook, the authors define distinct layout technique for quick frequency hopping synthesizers for RF and instant communications purposes. there's nice emphasis on fractional-N delta-sigma established part locked loops from standards, approach research and structure making plans to circuit layout and silicon implementation. The built ideas within the e-book will help in designing very low noise, excessive velocity fractional-N frequency synthesizers.
Read or Download CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation PDF
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Extra info for CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation
Gain and Noise Terms and their Units Gain terms Reference Divider R Charge pump Gain ICP Loop filter Z(s) VCO tuning gain KVCO PLL feedback Divider N Gain units No units Amps/rad Ω rad/V No units Noise terms Reference oscillator Phase noise Φr Charge pump Current noise Ipd Loop filter Voltage noise Vf VCO phase Noise ΦVCO Feedback Divider phase Noise Φn Output phase Noise Φout Noise units rad-rms or radrms/√Hz Amps or Amps/√Hz Volt or Volt/√Hz rad-rms or radrms/√Hz rad-rms or radrms/√Hz rad-rms or radrms/√Hz The notations used in Figure 3-10 are listed below.
Detailed description of those blocks is included in the appendices. 1 Phase-Frequency Detector The PFD  compares the divided down reference signal with the divided down feedback signal to generate a signal proportional to the phase error. Several types of frequency detectors are used in PLLs ; however, the most commonly used is the PFD as it offers both phase and frequency comparison. A conventional PFD is shown in Figure 3-2. The timing diagram for this PFD for the case of a reference signal lagging the VCO feedback signal is shown in Figure 3-3.
As can be seen from Figure 3-17, the ∆−Σ modulator emulates the average fractional part of the divider into instantaneous several integral levels. Those vary in a random manner between −7 and 8 for this order of modulator. In general, for Norder MASH modulator, the output would vary between –( 2 Norder − 1 ) and 2 Norder . Frac would then be emulated by instantaneous dividers that vary in a random manner between (N–( 2 Norder − 1 )) and ( N + 2 Norder ) Phase-Locked Loop Frequency Synthesizers 37 such that the average value of the sequence of those divisors is equal to the desired fractional-N divider value.