By Prakash Gopalakrishnan

Cell-based layout methodologies have ruled structure new release of electronic circuits. regrettably, the transforming into calls for for obvious technique portability, elevated functionality, and low-level equipment sizing for timing/power are poorly dealt with in a hard and fast cellphone library. Direct Transistor-Level format For electronic Blocks proposes a right away transistor-level structure technique for small blocks of customized electronic common sense as a substitute that greater incorporates calls for for device-level flexibility. This method captures crucial shape-level optimizations, but scales simply to netlists with hundreds of thousands of units, and contains timing optimization in the course of format. the major concept is early id of crucial diffusion-merged MOS gadget teams, and their upkeep in an uncommitted geometric shape until eventually the very finish of specified placement. approximately conversing, crucial teams are extracted early from the transistor-level netlist, put globally, optimized in the neighborhood, after which ultimately devoted every one to a particular shape-level shape whereas at the same time optimizing for either density and routability. the basic flaw in previous efforts is an over-reliance on geometric assumptions from large-scale cell-based format algorithms. person transistors could appear basic, yet they don't pack as gates do. Algorithms that forget about those shape-level concerns endure the implications while hundreds of thousands of units are poorly packed. The procedure defined during this publication can pack units even more densely than a standard cell-based structure. Direct Transistor-Level format For electronic Blocks is a accomplished reference paintings on device-level format optimization, with the intention to be useful to CAD software and circuit designers.

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We compile these into functional schematics using logic synthesis‚ which we then flatten to a transistor-level netlist. 1 Benchmark generation for Steps Logic description Tools / Method LGSynth91 benchmarks [CBL] Using SIS [Sentovich Logic synthesis 92] for logic synthesis. Simple target library containing INVERT/ AND/NAND/OR/NOR gates up to 4 inputs. Transistor-level flatten- Using scripts and transistor-level implementaing tions of library elements from target library. 18um STMicroelectronics process.

NetCost + w2 . GridCost + w3 . RowCost NetCost is evaluated as the sum of the half-perimeters of the netbounding boxes for all nets. This optimizes for wirelength. GridCost is used to legalize overlaps between the various modules. It is a ratio of the module widths at a particular grid-location to the capacity of the grid-location. RowCost is used to optimize for row-raggedness and also row-utilization. It is a measure of the variances between various row widths. This helps minimize the area of the layout.

Setting up objective function for quadratic solve procedure set_up_objective_function Initialize C = 0 , foreach net in Netlist, n wt = net_wt(n) * 2 / (num_pads(n) + num_modules(n)) foreach module connected to net n, foreach pad connected to net n, 16 17 18 19 20 21 22 23 end end end end 24 25 26 27 The vectors x and y represent the coordinates of the various clusters for the movable modules. The matrix C, also referred to as the modified connectivity matrix, and the vectors & are populated by the procedure set_up_objective_function, described in Figure 20.

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